【Data Transfer Instructions】
1. General data transmission instructions
1. Transmit command MOV(mov)
Assembly format of instruction: MOV DST, SRC Basic functions of instruction: (DST)<-(SRC) Transfer the original operand (byte or word) to the destination address. Addressing methods supported by instructions: The destination operand and the source operand cannot be addressed at the same time. This limitation applies to all instructions. The effect of the execution of the instruction on the flag bit: it does not affect the flag bit. Special requirements of instructions: the target operand DST and the source operand SRC are not allowed to be segment registers at the same time; the target operand DST cannot be CS, nor can it be used for immediate counting.
2. Push onto the stack instruction PUSH(push onto the stack)
The assembly format of the POP (pop from the stack) instruction: PUSH SRC; the basic functions of the POP DST instruction: PUSH instruction is often used in the program to temporarily store certain data, and the POP instruction can restore these data. PUSH SRC (SP)<-(SP)-2; (SP)<-(SRC) POP DST (DST)<-(SP)); (SP)<-(SP) The addressing methods supported by the push and pop instructions: the push and pop instructions cannot use the immediate addressing method. Effects of instructions on flag bits: neither PUSH nor POP instructions affect flag bits. Special requirements for instructions: PUSH and POP instructions can only be word operations, so after accessing word data, the modification of SP must be +2 or -2; the DST of the POP instructions is not allowed to be CS registers;
3. Exchange command XCHG(exchange)
Assembly format of instruction: XCHG OPR1,OPR2 Basic functions of instruction: (OPR1)<->(OPR2) Addressing method supported by instruction: One operand must be in the register, and the other operand can be in the register or memory. The movie of the command to the flag bit: does not affect the flag bit. Special requirements for instructions: Segment registers are not allowed.
2. Special transmission command for accumulator
4. Input command IN(input)
Output instruction OUT (output) The assembly format of the instruction: IN ac,port port<=0FFH IN ac,DX port>0FFH OUT port,ac port<=0FFH OUT DX,ac port>0FFH Basic functions of the instruction: For microprocessors of 8086 and its subsequent models, all I/O ports and CPU are completed by the input and output instructions IN and OUT. The IN instruction inputs information from I/O to the CPU, and the OUT instruction outputs information from the CPU to the I/O port. Therefore, both the IN and OUT instructions must indicate the I/O port address. IN ac,port port<=0FFH (AL)<-(port)Transfer bytes or (AX)<-(port+1,port)Transfer word IN ac,DX port>0FFH (AL)<-((DX))Transfer bytes or (AX)<-(DX)+1,(DX))Transfer word OUT port,ac port<=0FFH (port)<-(AL)Transfer bytes or (port+1,port)<-(AX)Transfer word OUT DX,ac port>0FFH (DX)<-(AL)Transfer bytes or ((DX)+1,(DX))<-(AX)Transfer word instruction affects the flag bit: does not affect the flag bit. Special requirements for instructions: only for transferring information between AL or AX and I/O ports. AX is used to transmit 16-bit information, and AL is used to transmit 8-bit information, depending on the width of the peripheral port.
5. Code-change command XLAT (translate)
Assembly format of instruction: Basic functions of XLAT opr or XLAT instruction: This instruction replaces the code in the byte table assigned by BX in the AL according to the displacement provided by the AL register. (AL)<-((DS)*16+(BX)+(AL))) The influence of the instruction on the flag bit: does not affect the flag bit. Special requirements of the instruction: The length of the built byte table cannot exceed 256 bytes, because the 8-bit register AL is stored in the displacement. opr is the first address of the table. Because the offset address represented by opr has been stored in the BX register, opr is optional in the code change instruction, and it improves the readability of the program.
3. Address transmission command
6. Effective address transmitter LEA (load effective address)
Instruction assembly format: LEA reg, basic function of src instruction: LEA instruction sends the valid address of the source operand to the specified register, and this valid address is determined by a memory addressing method selected by src. Addressing methods supported by instructions: various memory addressing methods. The influence of instructions on flag bits: does not affect flag bits. Special requirements for instructions: reg in the instruction cannot be a segment register;
7. Pointer send register and DS LDS (load DS with point)
Pointer send register and ES LES (load ES with point) instruction assembly format: LDS reg,src LES reg,src Basic functions of the instruction: LDS and LES instructions send offset address that determines the location of the memory cell to register, segment address DS or ES. This offset address and segment address (also known as address pointer) are provided by two successive word units specified by src. LDS reg,src (reg)<-(src) (DS)<-(src+2) LES reg,src (reg)<-(src) (ES)<-(src+2) Addressing methods supported by instructions: src must be memory addressing methods The influence of instructions on flag bits: does not affect flag bits. Special requirements for instructions: REG in instructions cannot be segment registers;
4. Flag register transmission instruction
8. The low byte of the flag register is sent to AH LAHF (load AH with FLAGS)
Assembly format of instruction: Basic functions of LAHF instruction: (AH)<-(FLAGS)0-7 The influence of instruction on flag bits: does not affect flag bits
9. Low byte of AH send flag register SAHF(store AH into FLAGS) instruction format: Basic functions of SAHF instruction: (FLAGS)0-7<-(AH) instruction influence on flag bits: The value of the flag bit is determined by loading the value.
10. The flag is put into the stack PUSHF(push the flags)
Assembly format of instruction: Basic functions of PUSHF instruction: (SP)<-(SP)-2 ((SP)+1,(SP))<-(FLAGS)0-15 The influence of instruction on flag bits: does not affect flag bits.
11. Flags are posted POP(pop the FLAGS)
Assembly format of instruction: Basic functions of POPF instruction: (FLAGS)0-15<-((SP)+1,(SP)) (SP)<-(SP)+2 The influence of instruction on flag bits: The load value determines the value of the flag bit.
【Arithmetic Instructions】
1. Additive instruction
12. Addition instruction ADD(addition)
Assembly format of instructions: add dst,src Basic functions of instructions: (dst)<-(src)+(dst) The addressing method supported by instructions: The two operands cannot be addressed to memory at the same time. That is, except for the case where the source operand is an immediate number, the source operand and destination operand must have a register addressing method. The influence of instructions on flag bits: SF=1 The addition result is a negative number (sign bit is 1) SF=0 The addition result is a positive number (sign bit is 0) ZF=1 The addition result is zero ZF=0 The addition result is not zero CF=1 The most significant bit has a carry to the high position CF=0 The most significant bit has no carry to the high position OF=1 The two same-signed numbers are added (positive number + positive or negative number + negative number), and the result symbol is the opposite. OF=0 Add two different symbol numbers, or add the same symbol numbers, and the result symbol is the same as them.
13. Bring in to add command ADC(add with carry)
Assembly format of instructions: ADD dst, src Basic functions of the instructions: (dst)<-(src)+(dst)+CF The addressing method supported by the instructions: The two operands cannot be addressed to memory at the same time. That is, except for the case where the source operand is an immediate number, the source operand and destination operand must have a register addressing method. The influence of instruction on flag bits: SF=1 The addition result is a negative number SF=0 The addition result is a positive number ZF=1 The addition result is zero ZF=0 The addition result is not zero CF=1 The most significant bit has carry to the high position CF=0 The least significant bit has no carry at the high position OF=1 The result symbol is added, and the result symbol is opposite to it, OF=0 The two numbers with the same symbol, or the same symbol is added, and the result symbol is the same
14. Add 1 instruction INC(increament)
Assembly format of instruction: INC opr Basic functions of instruction: (opr)<-(opr) Addressing method supported by instruction You can use any addressing method except the immediate method. The influence of the instruction on the flag bits: SF=1 The addition result is a negative number SF=0 The addition result is a positive number ZF=1 The addition result is zero ZF=0 The addition result is not zero OF=1 The result is two numbers with the same symbol are the opposite of them, and the result symbol is the same as them. OF=0 The two numbers with the same symbol are added, or the same symbols are added, and the result symbol is the same as them.
2. Subtraction instruction
15. Subtraction instruction SUB(subtract) instruction assembly format: SUB dst,src instruction basic functions: (dst)<-(dst)-(src) instruction supported addressing method: their two operands cannot address memory at the same time. That is, except for the case where the source operand is an immediate number, the source operand and destination operand must have a register addressing method. The influence of instructions on flag bits: SF=1 The subtraction result is a negative number (sign bit is 1) SF=0 The subtraction result is a positive number (sign bit is 0) ZF=1 The subtraction result is zero ZF=0 The subtraction result is not zero CF=1 The most significant bit in binary subtraction operation has borrowed bits to the high bit (the subtraction is less than the subtraction, and it is not reduced enough) CF=0 The most significant bit in binary subtraction operation is that there is no borrowing bits to the high bit (the subtraction is less than the subtraction, and it is not reduced enough) OF=1 The two numbers are opposite (positive number-negative number, or negative number-positive number), and the result symbol is the same as the subtraction. OF=0 When the same symbol number is subtracted, or when different symbol numbers are subtracted, the result symbol is different from the subtraction.
16. Subtract instruction with borrowing and subtraction instruction SBB(subtract with borrow)
Instruction assembly format: SBB dst, src Basic functions of the instructions: (dst)<-(dst)-(src)-CF instructions support addressing method: The two operands cannot address memory at the same time. That is, except for the case where the source operand is an immediate number, the source operand and destination operand must have a register addressing method. The influence of instructions on flag bits: SF=1 The subtraction result is a negative number (sign bit is 1) SF=0 The subtraction result is a positive number (sign bit is 0) ZF=1 The subtraction result is zero ZF=0 The subtraction result is not zero CF=1 The most significant bit in binary subtraction operation has borrowed bits to the high bit (the subtraction is less than the subtraction, and it is not reduced enough) CF=0 The most significant bit in binary subtraction operation is that there is no borrowing bits to the high bit (the subtraction is less than the subtraction, and it is not reduced enough) OF=1 The two numbers are opposite (positive number-negative number, or negative number-positive number), and the result symbol is the same as the subtraction. OF=0 When the same symbol number is subtracted, or when different symbol numbers are subtracted, the result symbol is different from the subtraction.
17. 1 decrement instruction DEC(decrement)
Assembly format of instruction: DEC opr Basic functions of the instruction: (opr)<-(opr)-1 Addressing method supported by the instruction: Any addressing method except the immediate method can be used. The influence of instruction on flag bits: SF=1 The subtraction result is a negative number (sign bit is 1) SF=0 The subtraction result is a positive number (sign bit is 0) ZF=1 The subtraction result is zero ZF=0 The subtraction result is not zero OF=1 The two numbers are opposite (positive-negative, or negative-positive), and the result symbol is the same as the subtraction. OF=0 When the same symbol number is subtracted, or when different symbol numbers are subtracted, the result symbol is different from the subtraction.
18. Comparison command CMP(compare)
Assembly format of instruction: CMP opr1,opr2 Basic functions of instruction: (opr1)-(opr2), set the condition code according to the subtraction result, but do not return the result. The addressing method supported by instructions: The two operands cannot address memory at the same time. That is, except for the case where the source operand is an immediate number, the source operand and destination operand must have a register addressing method. The influence of instructions on flag bits:
SF=1 The subtraction result is a negative number (sign bit is 1) SF=0 The subtraction result is a positive number (sign bit is 0) ZF=1 The subtraction result is zero ZF=0 The subtraction result is not zero CF=1 The binary subtraction operation is
The most significant bit has borrowed bits to the high bit (the subtracted is less than the subtracted, and it is not reduced enough) CF=0 The most significant bit in binary subtraction operation is that there is no borrowed bits to the high bit (the subtracted is >= subtracted, and it is deducted enough) OF=1 The two numbers are opposite (positive number-negative number, or negative number-positive number), and the result symbol is the same as the subtracted. OF=0 When the same symbol number is subtracted, or when different symbol numbers are subtracted, the result symbol is different from the subtraction.
19. Request for supplemental instructions NEG(negate)
Instruction assembly format: NEG opr Basic functions of the instruction: (opr)<- -(opr) Addressing method supported by the instruction: Any addressing method except the immediate method can be used. The influence of instructions on flag bits: CF=1 Search for operands that are not 0 CF=0 Search for operands that are 0 OF=1 The operand is -128 (byte operation) or the operand is -32768 (word operation) OF=0 When the operand for complement operation is not -128 (byte) or -32768 (word), 3. Multiplication instruction
20. Unsigned multiplication instruction NUL(unsigned multiple)
Signed multiplication instruction IMUL(signed muliple) instruction assembly format: NUL src IMUL src Basic functions of the instruction: (AX)<-(AL)*(src) (DX,AX)<-(AX)*(src) The addressing method supported by the instruction: src can use any addressing method except the immediate method. The influence of instructions on flag bits: The multiplication instruction only affects the flag bits CF and OF, and other conditional code bits are not defined. The condition code of the MUL instruction is set to: CF OF=0 0 The height of the product is 0 (byte operation (AH) or word operation (DX)) CF OF=1 1 The height of the product is not 0 The condition code of the IMUL instruction is set to: CF OF=0 0 The high of the product is the sign extension of the lower half. CF OF=1 1 Special requirements of other situation instructions: The difference between the MUL and IMUL instructions is only whether the operand is unsigned or signed. Their common point is that the instruction only gives the source operand src, the destination operand is implicit, and it can only be an accumulator (word operation is AX, byte operation is AL). The implicit product registers are AX or DX (high bit) and AX (low bit).
4. Symbol extension instructions
21. Sections are expanded to words CBW (convert byte to word)
Assembly format of instruction: CBW Basic functions of instruction: (AH)=00H When the most significant bit of (AL) is 0 (AH)=FFH When the most significant bit of (AL) is 1, the influence of instruction on flag bits: does not affect the special requirements of flag bit instructions: This is an instruction without operands, and the operands for symbol expansion must be stored in the AX register of the AL register.
22. Words are expanded to double word CWD (convert word to double word)
Assembly format of instruction: Basic functions of CWD instruction: (DX)=0000H When the most significant bit of (AX) is 0 (DX)=FFFH When the most significant bit of (AX) is 1, the influence of the instruction on the flag bit: does not affect the special requirements of the flag bit instruction: This is an instruction without operands, and the operands for symbol expansion must be stored in the AL register or the AX register.
V. Division instruction
23. Unsigned division DIV(unsigned divide) Signed division IDIV (singed divide) Assembly format of instruction: DIV src Basic functions of IDIV src instruction: word operation (AL)<-(AX)/src quotient (AH)<-(AX)/src remnant byte operation (AX)<-(DX,AX)/src quotient (DX)<-(DX,AX)/src quotient (DX)<-(DX,AX)/src remainder instruction supports addressing methods: src as a dividend, can be obtained by any addressing method except immediate number. The influence of instructions on flag bits: does not affect the condition code. Special requirements of instructions: When the division instruction requires that when the word operation, the dividend must be 32 bits, the divisor is 16 bits, and the quotient and remainder are 16 bits; when the byte operation, the dividend must be 16 bits, the divisor is 8 bits, and the quotient and remainder obtained are 8 bits.
6. Decimal adjustment instructions
【Logical Instructions】
1. Logical operations
Instruction format: ANDdst, src Basic functions of the instructions: (dst)<-(dst) and (src) The addressing method supported by the instructions: Both operands cannot be addressed to memory at the same time. That is, except for the case where the source operand is an immediate number, the source operand and destination operand must have a register addressing method. The influence of instructions on flag bits: CF and OF are set to zero after the instruction is executed, and AF is undefined. The result after the execution of the SF=1 instruction is negative (the sign bit is 1) SF=0 The result after the execution of the instruction is positive (the sign bit is 0) ZF=1 The result after the execution of the instruction is zero ZF=0 The result after the execution of the instruction is not zero PF=1 The result when the number of 1 in the result operand is even PF=0 The number of 1 in the result operand is odd PF=0 The number of 1 in the result operand is odd 25. Assembly format of the logic or OR(logic or) instruction: OR dst, the basic functions of the src instruction: (dst)<-(dst) or (src) Addressing method supported by the instruction: two operands cannot be addressed to memory at the same time. That is, except for the source operand being an immediate number, the original operand and the destination operand must have a register addressing method. The influence of instructions on flag bits: CF and OF are set to zero after the command is executed, and AF is undefined. SF=1 The result after the execution of the instruction is a negative number (the sign bit is 1) SF=0 The result after the execution of the instruction is a positive number (the sign bit is 0) ZF=1 The result after the execution of the instruction is zero ZF=0 The result after the execution of the instruction is not zero PF=1 Set 1 when the number of 1 in the result operand is even PF=0 Set 0 when the number of 1 in the result operand is odd 26. Logical non-NOT(logic not) Assembly format of the instruction: Basic functions of the instruction: (dst)<-(opr) Addressing method supported by the instruction: other addressing methods except for the immediate addressing method The influence of the instruction on the flag bit: no effect on the flag bit 27. XOR(exclusion or) Assembly format of the instruction: XOR dst,src Basic functions of instructions: (dst)<-(dst)Exor(src) The addressing method supported by the instructions: Two operands cannot be addressed to memory at the same time. That is, except for the source operand being an immediate number, the original operand and the destination operand must have a register addressing method. The influence of instructions on flag bits: CF and OF are set to zero after the command is executed, and AF is undefined. The result after the execution of the SF=1 instruction is negative (the sign bit is 1) SF=0 The result after the execution of the instruction is positive (the sign bit is 0) ZF=1 The result after the execution of the instruction is zero ZF=0 The result after the execution of the instruction is not zero PF=1 The result number of 1 in the operand is even PF=0 The result number of 1 in the operand is odd PF=0 The result number of 1 in the operand is odd 28. Test instruction Assembly format: TEST opr1,opr2 Basic functions of the instruction: (opr1) and (opr2) Addressing methods supported by the instruction: Two operands cannot be addressed at the same time, that is, except for the source operand being an immediate number, the source operand and the destination operand must have a register addressing method. The influence of instructions on flag bits: CF and OF are set to zero after the command is executed, and AF is undefined. SF=1 The result after the execution of the instruction is a negative number (the sign bit is 1) SF=0 The result after the execution of the instruction is a positive number (the sign bit is 0) ZF=1 The result after the execution of the instruction is zero ZF=0 The result after the execution of the instruction is not zero PF=1 Set 1 when the number of 1 in the result operand is even PF=0 Set 0 when the number of 1 in the result operand is odd
2. Shift command
29. Logical left shift SHL (shift logical left) instruction assembly format: SHL dst,cnt instruction basic function: SHL instruction moves cnt bit by bit to left. After each bit by bit, the lowest bit is supplemented by 0, and the highest displacement is transferred into CF. Addressing methods supported by instructions: the destination operand dst can be any addressing method except for immediate numbers. When the number of shifts (or number of bits) cnt=1, 1 can be written directly in the instruction. When cnt>1, cnt must be put into the CL register. The influence of instructions on flag bits: CF=moved value OF=1 When cnt=1, the value of the highest bit changes after the movement. OF=0 When cnt=1, the value of the highest bit does not change when moving. SF, ZF, PF is set according to the result after the movement
30. Logical right shift SHR (shift logical right) Assembly format of instruction: SHR dst,cnt Basic functions of instruction: SHR instruction moves cnt bit by bit to right. After each bit by bit, the highest bit is supplemented by 0, and the lowest bit is moved into CF. Addressing methods supported by instructions: the destination operand dst can be any addressing method except for immediate numbers. When the number of shifts (or number of bits) cnt=1, 1 can be written directly in the instruction. When cnt>1, cnt must be put into the CL register. The influence of instructions on flag bits: CF=moved value OF=1 When cnt=1, the value of the highest bit changes after the movement. OF=0 When cnt=1, the value of the highest bit does not change when moving. SF, ZF, PF are set according to the result after the movement. 31. Arithmetic left shift SAL(shift arithmetic left) instruction assembly format: SAL dst cnt instruction basic function: The SAL instruction moves cnt bit by bit to the left. After each bit by bit, the lowest bit is supplemented by 0, and the highest displacement is transferred into CF. Addressing methods supported by instructions: the destination operand dst can be any addressing method except for immediate numbers. When the number of shifts (or number of bits) cnt=1, 1 can be written directly in the instruction. When cnt>1, cnt must be put into the CL register. The influence of instructions on flag bits: CF=moved value OF=1 When cnt=1, the value of the highest bit changes after the movement. OF=0 When cnt=1, the value of the highest bit does not change when moving. SF, ZF, PF are set according to the result after the movement. 32. Arithmetic right shift SAR (shift arithmetic right) assembly format of instruction: SAR dst,cnt Basic functions of instruction: SAR commands move cnt bit by bit to right. After each bit by bit, the highest bit is supplemented by symbol bit, and the lowest bit is moved into CF. Addressing methods supported by instructions: the destination operand dst can be any addressing method except for immediate numbers. When the number of shifts (or number of bits) cnt=1, 1 can be written directly in the instruction. When cnt>1, cnt must be put into the CL register. The influence of instructions on flag bits: CF=moved value OF=1 When cnt=1, the value of the highest bit changes after the movement. OF=0 When cnt=1, the value of the highest bit does not change when moving. SF, ZF, PF are set according to the result after the movement. 33. Rotate left shift ROL (rotate left) assembly format of instruction: ROL The basic function of instruction: ROL The register or memory operand specified by dst is shifted left by the number of times specified by cnt, and each shifted left once, shifting the highest bit into the CF and operands at the same time. Addressing methods supported by instructions: the destination operand dst can be any addressing method except for immediate numbers. When the number of movements (or number of bits) cnt=1, 1 can be written directly in the instruction. When cnt>1, cnt must be put into the CL register. The influence of instructions on flag bits: CF=moved value OF=1 When cnt=1, the value of the highest bit changes after the movement. OF=0 When cnt=1, the value of the highest bit does not change when moving. SF, ZF, PF are set according to the result after the movement. 34. Rotate right ROR (rotate right) assembly format of instruction: ROR The basic function of the instruction: ROR The register or memory operand specified by dst is shifted right by the number of times specified by cnt, and move the lowest bit into the CF and operands at the same time. Addressing methods supported by instructions: the destination operand dst can be any addressing method except for immediate numbers. When the number of movements (or number of bits) cnt=1, 1 can be written directly in the instruction. When cnt>1, cnt must be put into the CL register. The influence of instructions on flag bits: CF=moved value OF=1 When cnt=1, the value of the highest bit changes after the movement. OF=0 When cnt=1, the value of the highest bit does not change when moving. SF, ZF, PF are set according to the result after the movement. 35. Rotate left through carry RCL (rotate left through carry) assembly format of instruction: RCL The basic function of the instruction: RCL The register or memory operand specified by dst, together with the carry flag CF, moves the number of times specified by m, and moves the highest displacement of the operand into CF every time left, and moves the original content in CF into the lowest bit of the operand. Specify supported addressing methods: the destination operand dst can be any addressing method except for immediate number. When the number of movements (or number of bits) cnt=1, 1 can be written directly in the instruction. When cnt>1, cnt must be put into the CL register. The influence of instructions on flag bits: CF = the value moved in. OF=1 When cnt=1, the value of the highest bit after movement has not changed. OF=0 When cnt=1, the value of the highest bit changes after movement. The SF, ZF, PF flag bits are not affected. 36. Rotate right through carry RCR (rotate right through carry) assembly format of instruction: RCR dst, cnt Basic functions of instruction: RCR For register or memory operands specified by dst, together with carry flag CF, the number of times specified by m, shifts the highest and lowest distance of the operand into CF, and the original content in CF is moved into the highest bit of the operand. Addressing methods supported by instructions: the destination operand dst can be any addressing method except for immediate numbers. When the number of movements (or number of bits) cnt=1, 1 can be written directly into the instruction. When cnt>1, cnt must be put into the CL register. The influence of instructions on flag bits: CF = the value moved in. OF=1 When cnt=1, the value of the highest bit of the operand has not changed. OF=0 When cnt=1, the value of the highest bit of the operand changes. The SF, ZF, PF flag bits are not affected.
【Serial Processing Instructions】
1. Set direction sign command
37. DF zero CLD(clear direction flag) DF set STD (set direction flag) Assembly format of instruction: CLD STD Basic functions of instruction: CLD DF=0 STD DF=1 2. String processing instructions 38. String transmission MOVSB / MOVSW(move string byte/word) Assembly format of instruction: MOVSB Basic functions of instruction: (ES:DI)<-(DS:SI) (SI)<-(SI)+/-1 (byte) or +/-2 (word) (DI)<-(DI)+/-1 (byte) or +/-2 (word) The influence of instruction on condition code: does not affect condition code. Special requirements for instructions: the source string must be in the data segment, the destination string must be in the additional segment, and the addressing method implicitly handled by the string instructions is the indirect addressing method of SI and DI registers. The source string allows segments to be specified using segment span prefix. 39. String STOSB / STOSW(stroe from string byte/word) instruction assembly format: STOSB The basic functions of the STOSW instruction: (ES:DI)<-(AL) or (AX) (DI)<-(DI)+/-1 (byte) or +/-2 (word) The influence of the instruction on the condition code: does not affect the condition code. Special requirements for instructions: the source string must be in the data segment, the destination string must be in the additional segment, and the addressing method implicitly handled by the string instructions is the indirect addressing method of SI and DI registers. The source string allows segments to be specified using segment span prefix. 40. Fetch string LODSB / LODSW(load from string byte/word) instruction assembly format: LODSB The basic functions of the LODSW instruction: (AL) or (AX)<-(DS:SI) (SI)<-(SI)+/-1 (byte) or +/-2 (word) The influence of the instruction on the condition code: does not affect the condition code. Special requirements for instructions: the source string must be in the data segment, the destination string must be in the additional segment, and the addressing method implicitly handled by the string instructions is the indirect addressing method of SI and DI registers. The source string allows segments to be specified using segment span prefix. 41. String comparison CMPSB / CMPSW(compare string byte/word) Assembly format of instruction: CMPSB Basic functions of CMPSW instruction: (DS:SI)-(ES:DI) Set condition code according to comparison results (SI)<-(SI)+/-1 (byte) or +/-2 (word) (DI)<-(DI)+/-1 (byte) or +/-2 (word) The influence of instruction on condition code: SF=1 The subtraction result is a negative number (sign bit is 1) SF=0 The subtraction result is a positive number (sign bit is 0) ZF=1 The subtraction result is zero ZF=0 The subtraction result is not zero CF=1 The most significant bit in binary subtraction operation has borrowed bits to the high bit (the subtraction is less than the subtraction, and it is not deducted enough) CF=0 The most effective binary subtraction operation is that there is no borrowing to the high position (the number is subtracted>= subtracted, enough to be subtracted) OF=1 The two numbers are opposite (positive number - negative number, or negative number - positive number), and the result symbol is the same as the subtracted. OF=0 When the same symbol number is subtracted, or when different symbol numbers are subtracted, the result symbol is different from the subtraction. 42. String scanning SCASB / SCASW(scan string byte / word) instruction format: SCASB Basic functions of SCASW instruction: (AL)<-(ES:DI) or (AX)<-(ES:DI) Set the condition code according to the results of the scan comparison. (DI)<-(DI)+/-1 (byte) or +/-2 (word) The influence of the instruction on the condition code: SF=1 The result is a negative number (sign bit is 1) SF=0 The result is a positive number (sign bit is 0) ZF=1 The result is zero ZF=0 The result is not zero CF=1 The most significant bit in binary subtraction operation has borrowed bits to the high position (the result is less than the subtraction, not enough to be reduced) CF=0 The most significant bit in binary subtraction operation is that there is no borrowing bits to the high position (the result is reduced>= subtraction, enough to be reduced) OF=1 The two numbers are opposite (positive-negative, or negative-positive), and the result symbol is the same as the subtraction. OF=0 When the same symbol number is subtracted, or when different symbol numbers are subtracted, the result symbol is different from the subtraction.
3. Repeat prefix for string
43. Repeat execution of string REP instruction assembly format: REP (CX)=The basic function of the repeating instruction: ① When (CX)=0, the string instruction is executed, otherwise ② ~ ④ ② (CX)←(CX)－1③ Execute string instruction (MOVS or STOS)④ Repeat execution① 44. Repeat execution of string instruction when equal/zero REPE/REPZ instruction assembly format: REPE / REPZ (CX)=The basic function of the comparison/scan instruction: ① When (CX)=0 or ZF=0, the string instruction is executed, otherwise continue ② ~ ④ ② (CX)←(CX)－1③ Execute string instruction (CMPS or SCAS)④ Repeat execution① 45. Repeat execution of string instruction when not equal/not zero Assembly format of REPNE / PEPNZ instruction: REPNE / PEPNZ (CX)=The basic functions of the command: ① (CX)=0 or ZF=1, end the execution of the string instruction, otherwise continue ② ~ ④ ② (CX)←(CX)-1③ Execute the string instruction (CMPS or SCAS)④ Repeat execution ①
【Control Transfer Instructions】
1. Unconditional transfer instructions
46. Short transfer JMP SHORT label(short jump) assembly format of instruction: basic functions of JMP SHORT label instruction: (IP)<-current (IP)+8-bit displacement The 8-bit displacement is automatically generated by the assembler when assembling the source program, based on the distance between the target address and the current IP. The influence of instructions on condition code: No effect on flag bits. 47. Near transfer JMP NEAR PTR label(near jump) Assembly format of instruction: Direct transfer JMP label (direct jump) Register indirect transfer JMP reg (register indirect jump) Memory indirect transfer JMP WORD PTR OPR (memory indirect jump) Basic functions of instruction: JMP label (IP) <- OFFSET label = (IP) Current +16-bit displacement JMP reg (IP) <- (reg) JMP WORD PTR OPR (IP) <- (PA+1,PA) Addressing methods supported by instructions: The steering address in the instruction can be direct addressing method, register addressing method, register indirect addressing method and memory addressing method. The influence of instructions on condition code: No effect on flag bits. 48. Far Transfer JMP FAR PTR label(for jump) assembly format: JMP FAR PTR label Basic functions of the instruction: (IP)<-label in-segment offset address (CS)<-label segment address of segment where the segment is located The instruction supports addressing method: The destination address of the far transfer can be represented by any addressing method except the immediate addressing method. The influence of instructions on condition code: No effect on flag bits.
2. Conditional transfer instructions
The assembly format and function of the instruction are transferred according to the value of the condition code: 49. JZ(JE) OPR ZF=1 ZF=0 (the operation result is 0, ZF is set to 1) 50. JNZ(JNE) OPR ZF=0 51. JS OPR SF=1 SF=0 (What is the highest bit in binary, what is SF, if the highest bit is 1, then SF=1) 52. JNS OPR SF=0 53. JO OPR OF=1 OF=1 (the two negative numbers add to positive numbers, overflow) 54. JNO OPR OF=0 55. JP OPR PF=1 PF=0 (the number that reflects the result "1", odd number ☞0 Even number ☞1) 56. JNP OPR PF=0 57. JC OPR CF=1CF=1 (the highest bit has a carry or borrowed position is set to 1) 58. JNC OPR CF=0 Compare two unsigned numbers and transfer according to the comparison result 59. JB(JNAE,JC) OPR CF=1 Transfer if the subtracted number is less than the subtracted number 60. JNB(JAE,JNC) OPR CF=0 Transfer if the subtracted number is greater than or equal to the subtract number 61. JBE(JNA) OPR CF or ZF=1 Transfer if the subtracted number is less than or equal to the subtract number 62. JNBE(JA) OPR CF or ZF=0 Transfer if the subtracted number is greater than the subtract number 60. JNBE(JA) OPR CF or ZF=0 Transfer if the subtracted number is greater than the subtract number 60. JNBE(JA) OPR CF or ZF=0 Transfer if the subtracted number is greater than the subtract number 60. JNBE(JA) OPR CF or ZF=0 Transfer if the subtracted number is greater than the subtract number 60. JNBE(JA) OPR CF or ZF=0 Transfer if the subtracted number is greater than the subtract number 60. JNBE(JA) OPR CF or ZF=0 Transfer if the subtracted number is greater than the subtract number 60. JNBE(JA) OPR CF or ZF=0 Transfer if the subtracted number is greater than the subtract number 60. JNBE(JA) OPR CF or ZF=0 Transfer if the subtracted number is greater than the subtract number 60. JNBE(JA) OPR CF or ZF=0 Transfer if the subtracted number is greater than the subtract number 60. JNBE(JA) OPR If the subtracted number is less than the minus, it will be transferred. 64. JNL/JGE SF Exclusive Or OF=0 If the subtracted number is not less than the minus, it will be transferred. 65. JLE/JNE (SF Exclusive Or OF) and ZF=1 If the subtracted number is not greater than the minus, it will be transferred. 66. JNLE/JG (SF Exclusive Or OF) and ZF=0 If the subtracted number is greater than the minus, it will be transferred according to the value of the CX register. 67. JCXZ (CX)=0 If the CX content is zero, the special requirements for the transfer instruction: All conditional transfer instructions are short transfer instructions, and the target address of the transfer must be within the range of -128 to +127 bytes of the current IP address. Therefore, the conditional transfer instruction is a 2-byte instruction.
3. Circular commands
68. Assembly format of loop LOOP(loop) instruction: Basic functions of LOOP label instruction: ① (CX)←(CX)-1 ② If (CX)≠0, then (IP)←(IP) is currently + displacement, otherwise the loop ends. Special requirements of instructions: cyclic instructions are all instructions in short transfer format, that is, the displacement is represented by 8-bit signed numbers, and the steering address is within the range of -128 ~ +127 bytes relative to the current IP value. 69. Loop when zero/equal LOOPZ/LOOPE(loop while nonzero or equal) instruction assembly format: LOOPNZ/LOOPNE label The basic functions of the instruction: ① (CX)←(CX)-1 ② If ZF=1 and (CX)≠0, then (IP)←(IP) is currently + displacement, otherwise the cycle ends. Special requirements of instructions: cyclic instructions are all instructions in short transfer format, that is, the displacement is represented by 8-bit signed numbers, and the steering address is within the range of -128 ~ +127 bytes relative to the current IP value. 70. Loop when not zero/unequal LOOPNZ/LOOPNE(loop while nonzero or not equal) instruction assembly format: LOOPNZ/LOOPNE label The basic functions of the instruction: ① (CX)←(CX)-1 ② If ZF=0 and (CX)≠0, then (IP)←(IP) is currently + displacement, otherwise the cycle ends. Special requirements of instructions: cyclic instructions are all instructions in short transfer format, that is, the displacement is represented by 8-bit signed numbers, and the steering address is within the range of -128 ~ +127 bytes relative to the current IP value.
4. Subprogram call
71. Directly close call CALL SUBROUT instruction in segment Basic functions: (SP)<-(SP)-2 ((SP)+1,(sp))<-(IP) (IP)<-(IP)+16-bit displacement amount Indirectly close call CALL DESTIN instruction in segment Basic functions: (SP)<-(SP)-2 ((SP)+1,(SP))<-(IP) (EA) 72. Directly call CALL FAR PTR SUBROUT instruction in segment Basic functions: (SP)<-(SP)-2,(SP))<-(CS)Current (SP)<-(SP)-2,(SP))<-(IP)Current (IP) <- Offset address (at the 2nd and 3rd bytes of the instruction) (CS) <- Segment address (at the 4th and 5th bytes of the instruction)
5. Return command
73. Return within the segment (near return) The basic functions of the RET instruction: (IP)<-((SP)+1,(SP)) (SP)<-(SP)+2 Return between segments (far return) The basic functions of the RET instruction: (IP)<-((SP)), (SP)<-(SP)+2 (CS)<-(SP)), (SP)<-(SP)+2 Return with immediate number RET N Perform operation: ① Return to the address (operation returns within the same segment or between segments)
② Modify the stack pointer: (SP) ← (SP) + N
6. Interrupt and interrupt return command
74. INT n interrupt instruction (interrupt), n is the interrupt type number to perform operations: ① Put the stack to save FLAGS: (SP) ← (SP)-2, ((SP)) ← (FLAGS) ② Put the stack to save return address: (SP) ← (SP)-2, ((SP)) ← (CS) (SP) ← (SP)-2, ((SP)) ← (IP) ③ Turn to interrupt handler: (IP) ← (n×4) (CS) ← (n×4+2) 75. IRET interrupt return instruction (return from interrupt) perform operations: ① Return address to release: (IP) ← ((SP)), (SP) ← (SP)+2 (CS) ← ((SP)), (SP) ← (SP)+2 ② FLAGS stack: (FLAGS) ← ((SP)), (SP) ← (SP)+2 76. INTO overflow is interrupted (interrupt type is 4) Perform operation: If OF=1 (there is overflow), then: ① Save FLAGS: (SP) ← (SP)-2, ((SP)) ← (FLAGS) ② Save return address: (SP) ← (SP)-2, ((SP)) ← (CS) (SP) ← (SP)-2, ((SP)) ← (CS) (SP) ← (SP)-2, ((SP)) ← (IP) ③ Transfer interrupt handler: (IP) ← (4×4)= (10H) (CS) ← (4×4+2)= (12H
HELLO, WORLD Advanced Assembler Series
Editor:admin Time:2004-3-21 12:49 Read:9785 Score:8 Print
Writer:LLUCT
Excelpt:80x86 assembly site
Preface：
Thanks to netizens lluct for providing originality for this site... suitable for beginners to learn
Content：
TITLE ***HELLO, the selection branch of WORLD advanced program BY LLUCT***
DATA SEGMENT ; defines data segments
MSG1 DB '***WELCOME TO MY PROGRAM BY LLUCT***','$'
;Define the first string information output. The string must be defined in DB, and $ is the end flag
MSG2 DB '1:BASIC MESSAGE 2:ADVANCED MESSAGE','$'
;Define the output string information: Select menu
MSG3 DB 'PLEASE CHOOSE:','$'
;Define the output string information: select the prefix
MSG4 DB 'HELLO,WORLD!^-^','$'
;Define the output string information: branch 1 information
MSG5 DB 'THIS IS MY FIRST ASM_86 PROGRAM! @^-^@','$'
;Define the output string information: branch 2 information
ERRMSG DB 'CHOOSE ERROR! -_-b','$'
;Define the output string information: select error information
DATA ENDS; end of data segment
CODE SEGMENT ; define code segments
ASSUME CS:CODE;Specify the content of CS
ASSUME DS:DATA; Specify the content of DS
START: MOV AX,DATA; The program starts with START
MOV DS,AX; DS setting initial value, DATA segment address
CALL ENTER ; Call the display carriage return line break subroutine
LEA DX, MSG1; output the offset address of the first string
CALL DISPCHS; call the display string subroutine
CALL ENTER ; Call the display carriage return line break subroutine
CALL ENTER ;This...same as above^-^
LEA DX, MSG2; output the offset address of the second string
CALL DISPCHS; call the display string subroutine
AGAIN: CALL ENTER; defines the AGAIN label. Used to select error cycles
LEA DX, MSG3; output the offset address of the third string
CALL DISPCHS; call the display string subroutine
MOV AH,01H; Call function No. 1: Enter a character from the keyboard and echo it
INT 21H; Complete input echo
CMP AL,'1'; Comparison of input characters with 1
JE BASICP; if equal, transfer to BASICP label (JE=Jump if Equal)
CMP AL,'2' ;Comparison of input characters with 2 ||
JE ADVANP; if equal, transfer to ADVANP label (JE= if equal, transfer)
JMP ERROR; otherwise it will be transferred to the ERROR label unconditionally
EXIT: MOV AH,4CH; Function call No. 4C: Terminate the current program and return to the calling program
INT 21H; Return to DOS
BASICP: CALL ENTER;What, I have to explain it. I'm dizzy-_-!!!
LEA DX, MSG4; output the offset address of the third string
CALL DISPCHS; call the display string subroutine
CALL ENTER ;..........
JMP EXIT; Unconditionally transfer to EXIT label
ADVANP: CALL ENTER ;55555555
LEA DX, MSG5; I explained it four times, I should understand
CALL DISPCHS; call the display string subroutine
CALL ENTER; I'll die for you to see if you ask again
JMP EXIT; Unconditionally transfer to EXIT label
ERROR: CALL ENTER
LEA DX,ERRMSG; output selection error message
CALL DISPCHS; call the display string subroutine
MOV DL,07H; output ASCII code alarm (ring) control character BEL(07H)
CALL DISPCH; Call to display a single character subroutine
CALL ENTER
JMP AGAIN
DISPCH PROC NEAR
; Display a single character subroutine, NEAR indicates that the subroutine and the main program are in the same code segment (there is no main program called)
MOV AH,02H; No. 2 function call: monitor output characters
INT 21H; Complete output display
RET ; return
DISPCH ENDP; end of subroutine
ENTER PROC NEAR; display carriage return line break subroutine
MOV DL, 0DH; Carriage return control character CR (0DH) output ASCII code
CALL DISPCH; Call to display a single character subroutine
MOV DL,0AH; newline control character LF (0AH) output ASCII code
CALL DISPCH; Call to display a single character subroutine
RET ; return
ENTER ENDP;End of subroutine
DISPCHS PROC NEAR
;Show string subroutine, NEAR indicates that the subroutine and main program are in the same code segment (there is no main program called)
MOV AH,09H; No. 9 function call: display string
INT 21H; Complete output display
RET
DISPCHS ENDP
CODE ENDS; End of code segment
END START;End assembly
;Copy the above code into a text program such as Notepad and save it. (For example)
;Compiled:masm
;Connection:link
;implement:
======================================================
title ***hello,world advanced string input and output by lluct***
data segment ; define data segments
input db 100 dup(?)
;Define the input string. The string must be defined in db and has a length of 100 bytes.
msg1 db 'Hello,','$'
;Define the output prefix string information. The string must be defined with db, and $ is the end flag (24h)
msg2 db ',Welcome to here!','$'
;Define the output suffix string information
headmsg db 'PLEASE INPUT YOUR NAME:','$'
;Stand information that begins to display
data ends; end of data segment
code segment ; define code segment
assume cs:code; stipulate the content of cs
assume ds:data ;Specify the content of ds
start: mov ax,data ;The program starts from start
mov ds,ax;ds set the initial value, the segment address of data
mov si,0; the initial value of the index register is 0
call enter; call display carriage enter line break subroutine
lea dx,headmsg; output the offset address of the string that starts to display
call dispchs ; call display string subroutine
repeat: mov ah,01h
;Define repeat label, used to input a single character in a loop. Call function No. 1: Enter a character from the keyboard and echo it
int 21h; Complete input echo
cmp al,0dh; Comparison of input characters with CR (Enter)
je exit ; if it is equal to Enter, it will be transferred to exit
mov input[si],al ; transfer the value of al to the si address of input (it seems to be the case)
inc si ;si plus 1
jmp repeat; unconditionally transfer to repeat
exit: call enter
mov input[si],24h; add the end flag ($) to the input completed string
call enter
lea dx,msg1; output the offset address of the prefix string
call dispchs ; call display string subroutine
lea dx,input; output the string just entered
call dispchs
lea dx,msg2
call dispchs
call enter
mov ah,4ch; 4c function call: terminates the current program and returns to the calling program
int 21h; return dos
enter proc near; display carriage return line break subroutine
mov dl,0dh; output ascii code carriage return control character cr(0dh)
call dispch
mov dl,0ah; newline control character lf(0ah) output ascii code
call dispch
ret ; return
enter endp; subroutine end
dispch proc near
mov ah,02h; No. 2 function call: monitor output characters
int 21h; Complete output display
ret ; return
dispch endp
dispchs proc near
mov ah,09h; function call No. 9: display string
int 21h; Complete output display
ret ; return
dispchs endp
code ends ; end of code segment
end start ; end assembly
;Copy the above code into a text program such as Notepad and save it. (For example)
;Compiled:masm
;Connection:link
;implement:
Interrupt refers to a reaction of the CPU to an event that occurs in the system: the CPU suspends the execution program, retains the site and automatically transfers to execute the corresponding processing program. After processing the event, it returns to the breakpoint to continue executing the "breaking" program.
In the computers we use, all hardware needs to perform interrupt request actions. Simply put, its function is to stop the working state of its related hardware. We can give an example in daily life to illustrate that if you are writing a letter to a friend and the phone rings, then you put down the pen in your hand to answer the phone, and then continue to write the letter after the call is over. This example shows the interruption and its handling process: the phone ringing makes you temporarily terminate your current work and deal with things that need to be handled more urgently - answering the phone, and after handling the urgently needed things, go back and continue with the original thing. In this example, the phone ringtone can be called an "interrupt request", and if you pause writing to answer the phone, it is called an "interrupt response", so the process of answering the phone is "interrupt processing". From this we can see that during the computer's execution of the program, due to a special situation (or "event"), the system temporarily aborted the current program and turned to execute the program that handles this special event. After processing, it returned to the original program's interrupt point and continued to execute downward, and this process is called interrupt.
The role of interruption
We can give another example to illustrate the role of interruption. Suppose a friend comes to visit you, but since you don’t know when you arrive, you can only wait at the door, so you can’t do anything. But if you install a doorbell at the door, you don’t have to wait at the door but can do other work at home. When a friend comes, he rings the doorbell to notify you, and then you interrupt the work in your hands and open the door, which avoids unnecessary waiting. The same is true for computers, such as printing documents. Because the CPU transmits data at a high speed and the printer is slow, if interrupt technology is not used, the CPU will often be in a waiting state, which will make the computer's work efficiency extremely low. After using the interrupt method, the CPU can perform other work while printing, and only respond after the current content in the printer buffer is printed and the interrupt request is issued. Only then can the current work be temporarily interrupted and the operation to stop printing is executed, and then return to execute the original program. This greatly improves the efficiency of the computer system.
irq interrupt
There are several types of interrupts in computers, and according to the source of interrupt signals, they can be divided into: hardware interrupts and software interrupts. Hardware interrupts are mostly issued by peripheral devices and computer system controllers, while software interrupts are generally generated by software commands. In hardware interrupts, there are also differences between "blockable interrupts" and "blockable interrupts". As the name suggests, blockable interrupts can be determined by the computer based on the needs of the system whether to perform reception processing or delay processing (i.e. blocking), while non-blockable interrupts are to directly activate the corresponding interrupt handler, which cannot and will not be delayed. The irq interrupt is a blockable hardware interrupt, and its full name is interrupt request, which is "interrupt request".
In a computer system, an interrupt controller 8259 or 8259a chip (most of the chips are now integrated into other chips) are used to control interruptions to each hardware in the system. Currently, there are 16 groups of irqs. If you remove the group of irqs used for bridging, there are actually only 15 groups of irqs for hardware calls. And these irqs have their own recommended configurations.
Allocate irq interrupts
The operating system we use daily has different settings for irq, so when installing new hardware, the system often cannot automatically detect the correct irq to allocate to the required hardware, which will cause this hardware device or the original old hardware to not work properly. In fact, this is the system that automatically allocates the irq of the hardware to other hardware that is the same as this irq, thus causing the hardware to not work properly. Generally, if you encounter this situation, you can solve it by manually adjusting the irq configurations of the new and old hardware.
For some commonly used hardware, they generally have their default irq values. For example, sound cards often use irq5 or 7. Although most of these accessories can work with other irq values, if you encounter particularly "picky" software or games and other programs, such as only identifying sound cards with irq values of 5 or 7, it will be useless to set it to irq9.
8.3.1 Basic concepts of interruption
Interrupt refers to an unusual or unexpected urgently needed event occurring in the system during implementation of the computer, causing the CPU to temporarily interrupt the currently executing program and transfer to the event handler to execute the response. After the pending process is completed, the process of returning to the original interrupt location to continue execution or dispatching the execution of a new program.
Modern computer systems generally have the ability to handle emergencies. For example: read a set of information from a tape. When it is found that there is an error in the read information, just let the tape return and reread the set of information, it is possible to overcome the error and obtain the correct information.
This ability to handle emergencies is accomplished in collaboration with hardware and software. First, the generated event is discovered by the hardware interrupt device, and then the interrupt device aborts the execution of the current program and leads to a program that handles the event for processing. The computer system can not only handle events arising from hardware or software errors, but also some kind of predetermined processing pseudo-event. For example: When the peripheral device is working, an interrupt request is also issued to report to the system that it has completed the task, and the system will handle it accordingly according to the specific situation. The event that causes an interrupt is called the interrupt source. Hardware that discovers an interrupt source and generates an interrupt is called an interrupt device. In different hardware structures, there are usually different interrupt sources and different interrupt devices, but they have one commonality: when an interrupt event occurs, the interrupt device can change the order in which operations are performed within the processor.
Interrupt source: The event that causes an interrupt is called an interrupt source. Interrupt request: The interrupt processing signal issued by the interrupt source to the CPU. Interrupt response: After the CPU receives the interrupt request, it transfers to the corresponding event handler. Disable interrupt (off interrupt): The interrupt allow bit of the processor status word PSW inside the CPU has been cleared, and the CPU is not allowed to respond to interrupts. On-interrupt: Setting the interrupt enable bit of PSW. Interrupt blocking: After the interrupt request is generated, the system selectively blocks part of the interrupt in software and allows the interruption of the part to still be responded.
8.3.4 Interrupt processing process
Interrupt processing process:
(1) The CPU checks whether the condition for responding to interrupt is met. The conditions for the CPU to respond to an interrupt are: there is an interrupt request from the interrupt source and the CPU allows an interrupt. If the interrupt response condition is not met, the interrupt processing cannot be performed. (2) If the CPU responds to an interrupt, the CPU is off and causes it to enter a state where the interrupt cannot be responded to again. (3) Save the interrupted process site. In order to enable the process to return to the interrupt point correctly after the interrupt processing is completed, the system must save the values of the current processor status word PSW and the program counter PC. These values are generally stored in a specific stack or hardware register. (4) Analyze the cause of the interrupt and call the interrupt processing subroutine. When multiple interrupt requests occur simultaneously, interrupt requests issued by the interrupt source with the highest priority are processed. (5) Execute the interrupt processing subroutine. For traps, in some systems, the corresponding processing subroutine is called after sending a soft interrupt signal to the current execution process through trap instructions. (6) Exit the interrupt, restore the site of the interrupted process or schedule a new process to occupy the processor. (7) Turn on interrupt and the CPU continues to execute.
1. What is interruption?
Simply put, an interrupt is an operation that causes the CPU to abort the executing program and transfer to handle special events. These events that cause interrupts are called interrupt sources, they may be input and output requests from peripherals, or they may be some abnormal accident or other internal causes of the computer. More specifically, we define CPU interrupts as a process: when a specific event (interruption source, also known as an interrupt request signal) triggers the CPU to suspend the running program (main program), and then first process a processing program written for a specific event (interruption handler), and wait until the interrupt handler is processed, then return to the place where the main program is interrupted to continue running.
2. The role of interruption
On the one hand, with the interrupt function, the PC system can enable the CPU and peripherals to work simultaneously, so that the system can respond to external events in a timely manner. And with the interrupt function, the CPU can allow multiple peripherals to work simultaneously. This greatly improves the CPU utilization rate and also improves the speed of data input and output. On the other hand, with the interrupt function, the CPU can promptly handle various software and hardware failures. During the operation of the computer, unexpected situations or some failures often occur, such as power supply failure, storage errors, operation overflow, etc. Computers can handle the interrupt system by themselves without having to shut down or report to staff.
3. Interrupt Type
In PC systems, interrupts are often divided into two categories according to the interrupt source: hardware interrupts and software interrupts. Hardware interrupts are also called external interrupts, and they can be divided into two types: 1). Maskable interrupt: is an interrupt caused by the interrupt request signal sent by the interrupt circuit that can be blocked by the CPU at the INTR end of the CPU. It is often generated by the peripherals of the PC or some interface functions, such as keyboards, printers, serial ports, etc. Maskable means that this type of interrupt can be blocked or ignored by the software when the CPU wants to handle other emergency operations. 2). Unmasked interrupt: It is an interrupt caused by the NMI side of the CPU. For example, when the system fails power or memory parity errors, the system will use unmasked interrupts. Non-mask means that the CPU cannot use software instructions to prohibit such interrupt response, that is, the CPU must respond to the interrupt signal sent by the NMI side. Software interrupt, also known as internal interrupt, refers to interrupts caused by using INT interrupt instructions in the program.
4. Conditions for CPU response interrupt
Except for non-blocking interrupts, other interrupts can be blocked or opened with software. Only when the system meets the following interrupt conditions can the CPU respond to the interrupt request. 1) Set interrupt request trigger 2) Set interrupt mask trigger 3) Set interrupt allow trigger
5. CPU processing interrupt process
When the interrupt condition is met, the CPU will respond to the interrupt and go to the interrupt program to process. The specific working process is as follows. 1) Off interrupt 2) Reserve breakpoint 3) Protect the site 4) Give the interrupt entrance and transfer to the corresponding interrupt service program 5) Restore the site 6) Turn on interrupt and return
6. Interrupt conflict
Although the Windows operating system has now supported plug-and-play since Win9X, which greatly simplifies users' operations, if the new device to be installed cannot be recognized, conflicts will arise when the interrupt is automatically allocated. Now new hardware products are emerging one after another, and various products are compatible with each other and have similar functions, which leads to the operating system often failing to correctly detect new devices, and interrupt conflicts are inevitable.
7. Structure of interrupt controller 8259A
The Intel 8259A is a programmable interrupt controller compatible with the 8088/8086 series. Later microcomputer systems also followed this interrupt mechanism and its functions, but because of the improvement of integrated chip technology, they did not appear alone in the form of 8259A chip, but were integrated into a chip called "South Bridge Chip" or "HUB Chip". 8259A includes the following parts: 1). Interrupt Request Register (Interrupt Request Register): There are 8 external interrupt request lines IR0~IR7, and each request line has a corresponding trigger to save the request signal. 2). Interrupt Service Register ISR (IN Service Register): Saves the interrupt being serviced. 3). Priority circuit: For each interrupt request stored in the IRR, the highest priority is determined after judgment, and it is gated to the interrupt service register during the interrupt response period. 4). Interrupt Mask Register (Interrupt Mask Register): Each bit in the register can block the corresponding interrupt source in the IRR. However, masking for input lines with higher priority does not affect inputs with lower priority. 5). Data bus buffer: It is the interface between 8259A and the system data bus, and it is an 8-bit bidirectional three-state buffer. All control words when the CPU programes 8259A are written to 8259A, and the 8259A status information is also read to the CPU through it; during the interrupt response period, the CALL instruction or interrupt vector sent to the data bus by 8259A is also transmitted through it. 6)． Read/write control logic: The CPU can use it to realize read (status signal) and write (initialization programming) to 8259A. 7). Cascade buffer: realizes cascade between 8259A chips, so that the interrupt source can be expanded from 8 to 64 levels. 8). Control logic part: controls the work inside the chip so that it works according to programming regulations.
8. The 8259A cascade in a system, 8259A can be cascaded, with a master 8259A, several slaves 8259A, and up to 8 slaves 8259A, expanding the interrupt source to 64.
Illegal transmission species
1. The types of the two operands are inconsistent -----For example, the source operand is bytes, and the destination operand is a word; or the other way around
• Most double operand instructions, unless otherwise specified, the target operand and the source operand must be of the same type, otherwise it is an illegal instruction MOV AL , 050AH; illegal instruction: 050Ah is a word, and AL is a byte
• Registers have clear byte or word types, and the operand type of the instruction with register participation is the type of register
• In case of memory cells as operands at the same time as immediate numbers, they must be explicitly specified;
byte ptr indicates byte type and word ptr indicates word type.
2. Both operands cannot be both memory --------------Transfer instructions are very flexible, but direct transmission between main memory is not allowed
• The 8086 instruction system does not allow both operands to be storage units (except serial operation instructions). To achieve this transmission, it can be implemented indirectly through registers.
mov ax , buffer1; ax←buffer1 (send buffer1 content to ax)
mov buffer2 , ax; buffer2←ax; here buffer1 and buffer2 are two word variables, and actually represent direct addressing method
3. There are some limitations on the operation of segment registers –----Segment registers are special registers and have limited operational capabilities.
• Immediate number transmission to segment registers is not allowed MOV DS,100H; Illegal instruction: Immediate number transmission cannot be performed
• Direct changes to CS value are not allowed MOV CS,[SI]; instructions that are not allowed
• Direct data transmission between segment registers is not allowed MOV DS,ES; Illegal instruction: transmission between segment registers is not allowed
MOV BL, AX (data length mismatch)
MOV DS, 2000H (Immediate assignment to segment memory is not allowed)
MOV CS, AX (It is prohibited to assign values to CS using MOV instructions)
MOV [AX], [2000H] (Directly transmitted between memory)
MOV [2000H], 20H (the data length is inaccurate, it should be changed to
MOV BYTE PTR [2000H],20H)
1. (1) Status flag: CF-carry flag, ZF-zero flag, SF-symbol flag, PF-parallel flag
OF - overflow flag, AF - auxiliary carry flag.
(2) Control mark: DF-direction mark, IF-interruption allow mark, TF-trap mark.
2. The 8086 machine code format is generally:
Opcode addressing method offsets are counted immediately.
3. (1) The source operand is immediate addressing, and the destination operand is register addressing.
(2) The source operand is register relative addressing, and the destination operand is register addressing.
(3) The source operand is register addressing, and the destination operand is register indirect addressing.
(4) The source operand and the destination operand are both fixed addressing.
4. This question requires a physical address. The calculation formula for the physical address is:
Segment address (segment head address) * 10H + offset address (valid address)
(1) The source operand is an immediate addressing method, and the operand address is in this instruction.
(2) The source operand is a direct addressing method, and its physical address is
DS*10H+100H=20100H
(3) The source operand is indirect addressing of registers, and its physical address is
SS*10H+BP=15010H
(4) The source operand is base addressing and its physical address is
DS*10H+BX+SI+VAL=201E0H
8086 has 14 16-bit registers. These 14 registers can be divided into four categories according to their purpose: (1) general register, (2) instruction pointer, (3) flag register and (4) segment register. (1) There are 8 general registers, which can be divided into 2 groups, one group is data register (4), and the other group is pointer register and index register (4). Data registers are divided into: AH&AL=AX(accumulator): accumulator register, commonly used for calculation; specified in multiplication and division instructions to store operands. In addition, all I/O instructions use this register to transmit data with external devices. BH&BL=BX(base): base register, commonly used for address indexing; CH&CL=CX(count): a count register, commonly used for counting; often used for storing calculated values, such as in shift instructions, loops (loops) and string processing instructions. DH&DL=DX(data): a data register, commonly used for data transfer. Their characteristics are that these 4 16-bit registers can be divided into high 8 bits: AH, BH, CH, DH. and low 8 bits: AL, BL, CL, DL. These 2 sets of 8-bit registers can be addressed separately and used separately. Another group is pointer register and index register, including: SP (Stack Pointer): a stack pointer, used in conjunction with SS, can point to the current stack position; BP (Base Pointer): a base pointer register, which can be used as a relative base address position of SS; SI (Source Index): a source index register can be used to store source index pointer relative to DS segment; DI (Destination Index): a destination index register, which can be used to store destination index pointer relative to ES segment. These four 16-bit registers can only be accessed in 16 bits, and are mainly used to form the address of the operand, which is used to calculate the effective address of the operand in stack operations and index operations. (2) Instruction Pointer IP (Instruction Pointer) The instruction pointer IP is a 16-bit dedicated register that points to the instruction byte that needs to be fetched. When the BIU fetches an instruction byte from memory, the IP will automatically add 1 to point to the next instruction byte. Note that IP points to the within-segment address of the instruction address, also known as the Offset Address or the Effective Address (EA). (3) Flag Register FR (Flag Register) 8086 has an 18-bit flag register FR, which has 9 bits meaningful in FR, where 6 bits are the status bits and 3 bits are the control bits. OF: The overflow flag bit OF is used to reflect whether the result of the signed addition and subtraction operation overflows. If the calculation result exceeds the range that can be represented by the current calculation number, it is called overflow, and the value of OF is set to 1, otherwise, the value of OF is cleared to 0. DF: The direction flag DF bit is used to determine the direction in which the pointer register is adjusted when the string operation instruction is executed. IF: The interrupt allow flag IF bit is used to determine whether the CPU responds to an interrupt request issued by a maskable interrupt outside the CPU. However, regardless of the value of this flag, the CPU must respond to interrupt requests issued by non-maskable interrupts outside the CPU and interrupt requests generated within the CPU. The specific provisions are as follows: (1) When IF=1, the CPU can respond to an interrupt request issued by a maskable interrupt outside the CPU; (2) When IF=0, the CPU does not respond to an interrupt request issued by a maskable interrupt outside the CPU. TF: Tracking flag TF. This flag can be used for program debugging. The TF flag has no special instructions to set or be clear. (1) If TF=1, the CPU is in the working mode of executing instructions in a single step. At this time, every time an instruction is executed, the current value of each register in the CPU and the next instruction that the CPU will execute is displayed. (2) If TF=0, it is in continuous working mode. SF: The symbol flag SF is used to reflect the symbol bit of the operation result, which is the same as the highest bit of the operation result. In microcomputer systems, signed numbers use complement representation, so SF reflects the positive and negative signs of the calculation result. When the calculation result is a positive number, the value of SF is 0, otherwise its value is 1. ZF: The zero flag ZF is used to reflect whether the calculation result is 0. If the calculation result is 0, its value is 1, otherwise its value is 0. This flag can be used when determining whether the calculation result is 0. AF: In the following cases, the value of the auxiliary carry flag AF is set to 1, otherwise its value is 0: (1) When the low byte carries or borrows to the high byte during word operation; (2) When the low 4 bits carry or borrows to the high 4 bits. PF: The parity flag PF is used to reflect the parity of the number of "1" in the calculation result. If the number of "1" is an even number, the value of PF is 1, otherwise its value is 0. CF: The carry flag CF is mainly used to reflect whether the operation produces carry or borrowed. If the highest bit of the calculation result produces a carry or borrow, then its value is 1, otherwise its value is 0. ) 4) Segment Register (Segment Register) In order to use all memory space, 8086 sets four segment registers, specifically used to save segment addresses: CS (Code Segment): Code Segment Register; DS (Data Segment): Data Segment Register; SS (Stack Segment): Stack Segment Register; ES (Extra Segment): Attached segment register. When a program is to be executed, it is necessary to decide which locations of memory to be used by the program code, data and stack, and point to these starting locations by setting segment registers CS, DS, and SS. Usually, the DS is fixed and the CS is modified as needed. Therefore, the program can be written to any size if the addressable space is less than 64K. Therefore, the size of the combined program and its data is limited to 64K as referred to by DS, which is why the COM file must not be larger than 64K. 8086 uses memory as the battlefield and registers as military base to speed up work.
Since 16-bit/32-bit CPUs are two important representatives of microcomputer CPUs, we will only introduce the names of their internal registers and their main functions.
1. 16-bit register group
The registers contained in the 16-bit CPU are
4 data registers (AX, BX, CX and DX)
2 index and pointer registers (SI and DI) 2 pointer registers (SP and BP)
4 segment registers (ES, CS, SS and DS)
1 instruction pointer register (IP) 1 flag register (Flags)
2. 32-bit register group
In addition to including all the registers of the previous CPU and expanding the general-purpose registers, instruction pointers and flag registers from 16-bit to 32-bit, the 32-bit CPU also adds 2 16-bit segment registers: FS and GS.
The registers contained in the 32-bit CPU are
4 data registers (EAX, EBX, ECX and EDX)
2 index and pointer registers (ESI and EDI) 2 pointer registers (ESP and EBP)
6 segment registers (ES, CS, SS, DS, FS and GS)
1 instruction pointer register (EIP) 1 flag register (EFlags)
Have one input port and two output ports.
The difference between macros and subprograms. Macros and subprograms are designed to simplify the writing of source programs and improve the maintainability of programs, but there are the following essential differences between them: 1. In the source program, macros are referenced by writing macro names, and subprograms are called through CALL instructions; 2. The assembler adds its definition body to the macro through macro expansion, and the number of times the macro is referenced will be expanded accordingly, so the referenced macros will not shorten the target program; and the subprogram code only appears once in the target program, and the call subprogram executes the same program segment, so the target program is also simplified accordingly; 3. When macros are referenced, parameters are passed by replacing "formal parameters" with "real parameters", and the parameters are flexibly and diverse. When subprograms are called, parameters are passed through registers, stacks or convention storage units; 4. After the macro reference statement is expanded, there will be no macro reference statements in the target program. There will be no additional time overhead when running, and the call of the subroutine still exists in the target program, and the call and return of the subroutine will take time. In short, when the program fragment is not long and speed is a key factor, macros can be used to simplify the source program, but when the program fragment is long and storage space is a key factor, subroutine methods can be used to simplify the source program and target program.
DATA SEGMENT
MSG1 DB
MSG2 DW
DATA ANDS
CODE SEGMENT
ASSUME CS:CODE，DS:DATA
START:MOV AX, DATA
MOV DS, AX
MOV DX OFFSET MSG1
( MOV BX
MOV AH, 4CH
INT 21H
CODE ENDS
END START
Regarding the role of assume, many people simply explain that this is telling the compiler which segment is associated with which segment register. To give a simple example: assumecs:code,ds:data This tells the compiler to associate cs with code, and ds with data. Later, I saw such code movax,data movds,ax, which made many people confused. Since ds and data are related, why do you have to send the data value to ds? What's going on? Here, let’s not explain too much, let’s take a look at the following example:
The following program copies the string in the data segment into the dseg segment, and calls the 9 function of the 21h interrupt of dos to display the string in the dseg segment:
; datasegment msgdb'Hello,howareyou?',0dh,0ah,24h dataends dsegsegment hellodb32dup(0) db0dh,0ah,24h dsegends codesegment assumecs:code,ds:dseg,es:data start: movax,dseg movds,ax; send the segment address of the dseg segment to ds movax,data moves,ax; send the segment address of the data segment to es movsi,offsetmsg; send the offset of the source string to si movdi,offsethello; send the offset of the target string to di cploop: moval,msg[si];(1) Here is a register relative addressing, so how is this physical address formed? cmpal,24h jzok movhello[di],al;(2) Here is another register relative addressing, how is this physical address formed? incsi incdi jmpshortcploop ok: movdx,offsethello movah,9h int21h movax,4c00h int21h codeends endstart
Let's analyze the formation of two addresses in (1) and (2): These two are register relative addressing, that is, the effective address is a register plus a 16-bit offset. For (1) EA=(si)+msg offset address The physical address is: (segment register) × 16+EA There are four cs, ds, es, ss in the segment register, so how does the compiler know which one to use? Here the role of assume is shown. Assume tells the compiler that the segment address of the label in the data segment should be obtained from es, that is, this sentence: es:data tells the compiler that all labels between datasegment and dataends should be addressed using es as the segment register. So when the compiler sees the msg label, it knows that the formation of the physical address here is (es)×16+EA. Similarly, for (2), when the compiler sees the hello label, it knows that the value in ds should be taken as the segment address. If there is no assume indicating which segment is associated with which register, the compiler cannot determine which segment register is used to calculate the physical address.
From here, we can also see that the function of assume is only to tell the compiler that when I encounter a label, when I want to calculate its physical address, the segment value is taken from which segment register. As for whether the value of this segment register is correct, it doesn't care. This is the program's business. Anyway, it only cares about using segment registers based on the settings in assume. Therefore, for programmers, not only should we use assume to tell the compiler which segment register to obtain the value when calculating the physical address, but also to clearly send the segment value of the corresponding segment to the set segment register in the instruction. Use the pseudo-instruction assume to tell the compiler that the segment address of the label in the data segment should be taken from es, while the instruction movax,data moves,ax sends the segment address of the data segment into es. In this way, the compiler can obtain the correct segment address when calculating the physical address of the msg label.
Of course, if you don't use assume to indicate which segment is associated with which register, for example, I changed assumecs:code,ds:dseg,es:data to assumecs:code, which is OK, that is, I do not associate ds with dseg, nor es with data, but you must clearly tell the compiler which segment register to use in the instruction. The instruction moval,msg[si] must be changed to moval,es:msg[si], and the instruction movhello[di],al must also be changed to movds:hello[di],al, so that the compiler can know which segment register to use to calculate the physical address. If the compiler cannot determine the segment address of the label, the program will not be compiled.
Summarize
The above is the detailed explanation and usage of various instructions for assembly language introduced by the editor. I hope it will be helpful to everyone!