With the speed of Ethernet 10 times each time, the structured wiring level of enterprises and operators has undergone a similar transformation. The maximum speed provided is still trapped by small quantity and high price, which is related to the task of the backbone network. Transfer to high-density aggregation switch at a mature rate where multiple links converge into distribution cabinets or central offices.
Design engineers closely monitor 100Gbps Ethernet, but the legacy transceiver modules and physical layer chips developed for 10Gbps links have also been bothering them. From a partial perspective, this is a reflection of the series and parallel disputes that have plagued fiber optic communications since the 1980s. The IEEE 802.3 Ethernet Working Group has always been to expand the bandwidth of the network, and thus approved various physical layer standards for different applications.
In many cases, these standards help to coexist with twisted pair copper wire, coaxial cable and fiber optics. However, in 10Gbps Ethernet, that means that the transceiver will be in many package types, including X2, Xenpak, Xpak and XFP, none of which meet the tiny footprint requirements of the small form factor pluggable (SFP) package originally designed for the Fibre Channel market. To this end, Ethernet supporters have stepped out of IEEE and returned to the T11 technical committee of the National Standards Association to seek new ideas for module development. From this they proposed the SFP+ format of T11.
In metro Ethernet applications, 10Gbps transceiver connected to XFP is generally used. The SFP+ format can be used to reduce it to the size of SFP and is used in 2.5Gbps networks. To achieve this, logic chips (such as electron scatter compensation EDC and clock/data recovery chips) that are usually embedded in the module with optoelectrons are placed in the user card and outside the transceiver.
"If I were to wrap the maximum number of 10Gbps ports in a pizza box-like format, I probably wouldn't care if the transceiver is fully integrated, and the more important question is to bring the 10Gbps channel into small spaces in the most efficient and cost-effective way," said Vidya Sharma, president of market space at transceiver supplier Picolight.
Rethinking the benefits of optical interconnects both components suppliers and OEMs, Todd Swenson, vice president of sales and marketing at Finisar, said it was hard to justify the continued inventory of X2, Xenpak and XFP modules, saying: "SFP+ may not be a fascinating solution, but it is agreed that the crazy pursuit of form factor appreciation is time to end."
In addition to reducing the space of the transceiver, SFP+ has many other meanings. Tom Marrapode, marketing director at Molex, pointed out that SFP+ may fundamentally change the board layout and routing of user cards and switch processors, because it uses high-speed serial wiring on the board to replace multiple parallel implementations (usually 4 2.5Gbps channels). Molex demonstrated a board at the Optical Fiber Communication Conference recently, allowing design engineers to see different packaging types, cabling lengths and diverse architectures designed for 10Gbps.
Placing certain electronic parts outside the transceiver module may allow for more efficient use of scatter compensation and clocking functions, as one device can serve multiple ports. Newly entered the road ClariPhy Communications is using SFP+ to design its EDC chips to take a unique approach in the scattering compensation markets that are strongly attacked by Scintera, Applied Micro Circuits (AMCC), Infinera and others. ClariPhy will design SFP+ into the emerging Ethernet market, including LRM, long-distance standard modules for multimode fibers, and LR and SR standard modules for long/short-distance single-mode fibers.
ClariPhy CEO observed that people have long assumed that a "silicon optical reference" model should be used to tightly integrate optical interfaces with photonic components and semiconductor devices, but channel equalization has become an unsolvable problem in newer modules such as XFP.
Legacy modules
The transceiver industry is still using Xenpak and Xpak/X2 modules, which use internally designed 4-bit parallel Xaui (10G additional unit interface). In the 1990s, this design seemed to make sense for user card wiring, because it was easier to handle 2.5Gbps wiring on a circuit board than to handle 10Gbps serial wiring. But signal conditioning technology pioneered by Broadcom and others breaks this balance.
The Xenpak module has the largest and most power-consuming, with a shape of 4.8×1.4×0.7 inches and a power consumption of 11W. The Xenpak is large enough to fit directly into the PCI bus interface and can be installed on a short PCI card. The Xpak is reduced to 2.7×1.4×0.4 inches and its power consumption is reduced to 4W.
XFP is the first module to use a 10Gb serial XFI internal interface instead of 4 2.5Gb channels. In many user cards, XFP still needs to be used with a serializer/deserializer because it is difficult to walk the 10Gb signal line on the board, although the situation is changing. XFP is similar to Xpak, but XFP is thinner, only 0.7 inches; power consumption is reduced to 2W, but this power consumption does not include the power consumption of the serializer/deserializer. XFP has become the darling of long-distance edge and metropolitan systems, but because the compound cost of XFP and Serdes is no different from the cost of Xpak, the large-scale shift to XFP user cards has not occurred.
The main factor driving the development of SFP+ is low power consumption. In an introduction to the T11, Redfern Integrated Optics demonstrates how to reduce static power consumption from 1W of XFP to 0.6W of SFP+ in a 1,550nm SFP+ design, so the active transmit power can be reduced from 2W to 1W.
For a time, innovative companies such as BitBlitz Communications (acquired by Intersil in 2004) managed to replace stack modules and short-range server clusters with 4-channel coaxial cables. The CX-4 standard was originally intended to use a Xaui interface to cooperate with 4 pairs of shielded twisted pair cables, but most OEMs and data center IT managers refuse to do any media rating between structured twisted pair copper wires (5E or Class 6) and multimode fibers.
The T11 Technical Committee in ANSI has been working for several quarters to turn SFP+ into a transmission tool for 4Gbps and 8Gbps Fibre Channel. As many storage area network developers turn to Ethernet framing protocols, it makes sense for Ethernet design engineers to attend the T11 conference and discuss SFP+.
But Finisar Swenson said: "It is not easy to replace the entire X series product. There are many issues to consider, such as what kind of user card or exchange card are you designing? What functions are you going to implement? The trade-offs on transceivers are similar to those of fiber or copper wire, and there is no conclusion yet."
Neal Neslusan, director of transmission marketing at Applied Micro Circuits, noted that many early solutions based on XFP and other X-derived products will still be feasible in WAN markets such as metro and edge access. “But the reason for focusing on SFP+ is that,” he said. “When enterprise networks consider LANs, servers and distributed groups, the increase in the number of applications of 10Gb Ethernet in enterprise networks will cause the WAN market to shrink. Whenever a dominant device vendor makes a choice about the interface, it will drive the industry; Cisco is adopting SFP+ in enterprise networks, which will have an impact not only on workgroup switching, but also on server interfaces.”
The tendency to separate certain chip functions from optical modules does not have a big impact on AMCC, Neslusan noted that the company's clock/data recovery design in XFP modules has not been successful. AMCC has several Serdes designs using XFP, but Serdes devices have been placed outside the XFP interface module.
"Indeed, as SFP+ enters the design, there will be more and more designs that go directly to the 10Gb wiring on the user card, but this is contrary to chip suppliers trying to design a 10Gb serial interface into ASICs. What we are seeing is that our Serdes chips are separated from the user card and installed on the motherboard so that people can retain the parallel interface of their control logic without having to bear the pain and cost of redesigning the ASICs."